US 12,218,139 B2
Semiconductor device with metal structure
Jhon Jhy Liaw, Zhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Dec. 30, 2021, as Appl. No. 17/566,082.
Claims priority of provisional application 63/172,926, filed on Apr. 9, 2021.
Prior Publication US 2022/0328526 A1, Oct. 13, 2022
Int. Cl. H01L 27/118 (2006.01)
CPC H01L 27/11807 (2013.01) [H01L 2027/11887 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of gate structures, wherein a first gate structure of the plurality of gate structures is arranged to be a first gate terminal of a first transistor, and wherein a second gate structure of the plurality of gate structures is arranged to be a second gate terminal of a second transistor;
a plurality of first metal layer structures formed above the plurality of gate structures, wherein each of the plurality of first metal layer structures and one of the plurality of gate structures are crisscrossed from a top view, and wherein each of the plurality of first metal layer structures have a first thickness T1;
a plurality of second metal layer structures formed above the plurality of first metal layer structures, wherein each of the plurality of second metal layer structures and one of the plurality of first metal layer structures are crisscrossed from the top view, and wherein each of the plurality of second metal layer structures have a second thickness T2; and
a plurality of third metal layer structures formed above the plurality of second metal layer structures, wherein each of the plurality of third metal layer structures and one of the plurality of second metal layer structures are crisscrossed from the top view, wherein each of the plurality of third metal layer structures have a third thickness T3, wherein the second thickness T2 is greater than both the first thickness T1 and the third thickness T3; and
a drain contact directly contacting both a drain feature of the first transistor and a drain feature of the second transistor together, wherein the drain contact is longer than each of a first source contact of the first transistor and a second source contact of the second transistor.