| CPC H01L 27/0924 (2013.01) [H01L 21/28525 (2013.01); H01L 21/76831 (2013.01); H01L 21/76897 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/167 (2013.01); H01L 29/41791 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/28518 (2013.01); H01L 21/31116 (2013.01); H01L 21/76805 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/665 (2013.01); H01L 29/7848 (2013.01); H01L 2029/7858 (2013.01)] | 20 Claims |

|
1. A device comprising:
a semiconductor fin extending from a substrate;
a gate structure extending across the semiconductor fin;
source/drain structures on opposite sides of the gate structure; and
a contact structure over a first one of the source/drain structures, the contact structure comprising a semiconductor contact and a metal contact over the semiconductor contact, wherein the semiconductor contact has a higher dopant concentration than the first one of the source/drain structures, and the first one of the source/drain structures comprises a first portion and a second portion at opposite sides of the semiconductor fin and interfacing the semiconductor contact, wherein the semiconductor contact forms an interface with a top surface of the semiconductor fin.
|
|
9. A device comprising:
an n-type transistor comprising a first fin extending from a substrate, a first gate structure extending across the first fin, first epitaxial structures on opposite sides of the first gate structure, and a first silicide region over one of the first epitaxial structures; and
a p-type transistor comprising a second fin extending from the substrate, a second gate structure extending across the second fin, second epitaxial structures on opposite sides of the second gate structure, and a second silicide region over one of the second epitaxial structures, wherein the second silicide region interfaces the second fin, and the first silicide region is spaced apart from the first fin, wherein the first epitaxial structures of the n-type transistor have a height higher than a height of the second epitaxial structures of the p-type transistor.
|
|
15. A device comprising:
an n-type transistor comprising a first fin extending from a substrate, a first gate structure extending across the first fin, and n-type source/drain structures on opposite sides of the first gate structure;
a p-type transistor comprising a second fin extending from the substrate, a second gate structure extending across the second fin, and p-type source/drain structures on opposite sides of the second gate structure;
a first silicide region above one of the n-type source/drain structures; and
a second silicide region above one of the p-type source/drain structures, wherein the second silicide region interfaces the second fin, but the first silicide region is spaced apart from the first fin.
|