US 12,218,135 B2
Wiring in diffusion breaks in an integrated circuit
Lars Liebmann, Albany, NY (US); Jeffrey Smith, Albany, NY (US); Daniel Chanemougame, Albany, NY (US); and Paul Gutwin, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Jan. 13, 2022, as Appl. No. 17/647,938.
Prior Publication US 2023/0223404 A1, Jul. 13, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 27/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 27/0688 (2013.01); H01L 29/4236 (2013.01); H01L 29/42392 (2013.01); H01L 29/785 (2013.01); H01L 2029/7858 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first three dimensional (3D) transistor and a second 3D transistor disposed in a substrate, the second 3D transistor oriented parallel to the first 3D transistor, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors;
a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction; and
a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire, wherein the diffusion-break wire comprises an insulating outer liner and a first conductive core electrically insulated from the first 3D transistor and the second 3D transistor by the outer liner.