US 12,218,133 B2
Three-dimensional semiconductor device and method of fabricating the same
Sungil Park, Suwon-si (KR); Jae Hyun Park, Hwaseong-si (KR); Daewon Ha, Seoul (KR); and Kyuman Hwang, Daejeon (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 3, 2022, as Appl. No. 17/805,261.
Claims priority of application No. 10-2021-0145770 (KR), filed on Oct. 28, 2021.
Prior Publication US 2023/0138121 A1, May 4, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823857 (2013.01); H01L 21/823878 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor device, comprising:
a first active region on a substrate, the first active region including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction;
a second active region on the first active region, the second active region including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction;
a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns; and
a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns,
wherein the first gate electrode includes:
a first lower gate electrode on the first lower channel pattern; and
a first upper gate electrode on the first upper channel pattern,
wherein the first lower gate electrode and the first upper gate electrode are connected to each other,
wherein the second gate electrode includes:
a second lower gate electrode on the second lower channel pattern;
a second upper gate electrode on the second upper channel pattern; and
an isolation pattern between the second lower gate electrode and the second upper gate electrode, and
wherein the second lower gate electrode and the second upper gate electrode are separated from each other by the isolation pattern.