US 12,218,132 B2
Integrated circuit
Guo-Huei Wu, Tainan (TW); Po-Chun Wang, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Chih-Liang Chen, Hsinchu (TW); and Li-Chun Tien, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 7, 2022, as Appl. No. 17/834,752.
Application 17/834,752 is a division of application No. 16/806,978, filed on Mar. 2, 2020, granted, now 11,374,003.
Claims priority of provisional application 62/833,464, filed on Apr. 12, 2019.
Prior Publication US 2022/0302111 A1, Sep. 22, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 23/538 (2006.01); H01L 29/06 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 23/5384 (2013.01); H01L 29/0649 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a multilayer stack, wherein the multilayer stack includes a plurality of first semiconductor layers and a plurality of second semiconductor layers that are alternately stacked;
forming a side portion of the plurality of first semiconductor layers by connecting, along a vertical direction, layers in the plurality of first semiconductor layers in a first portion of the multilayer stack to be a first semiconductor structure;
forming a first source region and a first drain region on opposing sides of the first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack;
removing the plurality of second semiconductor layers in the multilayer stack;
forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack;
forming a first insulating layer above the first gate region; and
forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.