| CPC H01L 27/0886 (2013.01) [H01L 21/76224 (2013.01); H01L 29/42372 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a first active region and a second active region spaced apart from each other;
an isolation region on side surfaces of the first and second active regions;
a first gate structure overlapping the first active region and the isolation region;
a second gate structure overlapping the second active region and the isolation region; and
a gate separation region between the first gate structure and the second gate structure,
wherein the first gate structure includes a first gate dielectric layer, a first gate electrode on the first gate dielectric layer and a first capping layer on the first gate electrode,
wherein the second gate structure includes a second gate dielectric layer, a second gate electrode on the second gate dielectric layer and a second capping layer on the second gate electrode,
wherein each of the first and second gate structures has a line shape or bar shape in a first direction,
wherein the first gate structure and the second gate structure are spaced apart from each other in the first direction,
wherein the first gate structure, the gate separation region and the second gate structure are sequentially arranged in the first direction,
wherein a lower end of the gate separation region is at a lower level than lower surfaces of the first and second gate structures adjacent to the gate separation region,
wherein the gate separation region includes:
a lower insulating layer between the first gate electrode and the second gate electrode; and
an upper insulating layer between the first capping layer and the second capping layer,
wherein a material of the upper insulating layer is different from a material of the lower insulating layer, and
wherein a lower surface of the gate separation region has a rounded shape.
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