US 12,218,130 B2
Semiconductor structure cutting process and structures formed thereby
Chih-Chang Hung, Hsinchu (TW); Chia-Jen Chen, Hsinchu (TW); Ming-Ching Chang, Hsinchu (TW); Shu-Yuan Ku, Zhubei (TW); Yi-Hsuan Hsiao, Taipei (TW); and I-Wei Yang, Yilan County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 1, 2023, as Appl. No. 18/526,290.
Application 16/407,730 is a division of application No. 15/860,492, filed on Jan. 2, 2018, granted, now 10,867,998, issued on Dec. 15, 2020.
Application 18/526,290 is a continuation of application No. 17/872,417, filed on Jul. 25, 2022, granted, now 11,855,085.
Application 17/872,417 is a continuation of application No. 17/085,121, filed on Oct. 30, 2020, granted, now 11,444,080, issued on Sep. 13, 2022.
Application 17/085,121 is a continuation of application No. 16/407,730, filed on May 9, 2019, granted, now 10,833,077, issued on Nov. 10, 2020.
Claims priority of provisional application 62/591,898, filed on Nov. 29, 2017.
Prior Publication US 2024/0113113 A1, Apr. 4, 2024
Int. Cl. H01L 27/088 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/283 (2013.01); H01L 21/31116 (2013.01); H01L 21/32136 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/42376 (2013.01); H01L 29/49 (2013.01); H01L 29/4991 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/78 (2013.01); H01L 21/02068 (2013.01); H01L 21/31053 (2013.01); H01L 21/31144 (2013.01); H01L 21/3212 (2013.01); H01L 21/32139 (2013.01); H01L 29/6656 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first gate structure over a first active area and a second active area on a substrate, a dielectric layer being disposed along opposing sides of the first gate structure;
performing a first etch process to form a first recess in the first gate structure and the dielectric layer;
performing a second etch process to laterally widen the first recess, wherein after the second etch process, a width of the first recess in the first gate structure is wider along a first line parallel to a longitudinal axis of the first gate structure than a width of the first recess in the dielectric layer along a second line parallel to the first line; and
filling the first recess with a dielectric material.