| CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823878 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/0649 (2013.01)] | 20 Claims |
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1. A method for manufacturing a semiconductor device, comprising:
forming a pair of sacrificial gate structures over channel regions formed over a substrate, each of the pair of sacrificial gate structures including a sacrificial gate electrode layer, a sacrificial gate dielectric layer and sidewall spacer layers disposed on both sides of the sacrificial gate electrode layer;
forming interlayer dielectric layers at both sides of the pair of sacrificial gate structures;
patterning the pair of sacrificial gate structures and the interlayer dielectric layers so that the pair of sacrificial gate structures are divided into at least a first sacrificial gate structure and a second sacrificial gate structure separated by a separation opening and a third sacrificial gate structure and a fourth sacrificial gate structure separated by the separation opening;
forming a separation wall by filling the separation opening with a first insulating material and a second insulating material different from the first insulating material, wherein a part of the second insulating material of the separation wall is in direct connection with the interlayer dielectric layers;
removing the sacrificial gate electrode layer and the sacrificial gate dielectric layer from the first to fourth sacrificial gate structures, so that a first electrode space and a second electrode space are formed and the separation wall is exposed between the first electrode space and the second electrode space and a third electrode space and a fourth electrode space are formed and the separation wall is exposed between the third electrode space and the fourth electrode space; and
forming a first gate structure, a second gate structure, a third gate structure and a fourth gate structure in the first electrode space, the second electrode space, the third electrode space and the fourth electrode space, respectively,
wherein, during the removing the sacrificial gate dielectric layer, portions of the first insulating material exposed to the first to fourth electrode spaces are removed.
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