| CPC H01L 27/0266 (2013.01) [H02M 7/539 (2013.01)] | 9 Claims |
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1. A circuit for discharging electrostatic, comprising:
a voltage-dividing circuit electrically coupled to a voltage input terminal that is configured to receive a power signal, so as to generate a detection signal at a voltage-dividing terminal;
a first inverter configured to receive and invert the detection signal to output an inverted detection signal;
a voltage boosting circuit comprising:
a first PMOS circuit and a first NMOS circuit electrically coupled in series between the voltage input terminal and a ground terminal through a first terminal, wherein the first PMOS circuit comprises a first PMOS control terminal electrically coupled to a second terminal and the first NMOS circuit comprises a first NMOS control terminal configured to receive the inverted detection signal; and
a second NMOS circuit electrically coupled between the second terminal and the ground terminal and comprising a second NMOS control terminal configured to receive the detection signal;
a first circuit comprising a resistive circuit for providing resistance that is electrically coupled between the voltage input terminal and a control terminal and a capacitive circuit for providing capacitance that is electrically coupled between the control terminal and a ground terminal, wherein the control terminal is electrically coupled to the second terminal;
a second inverter electrically coupled between the voltage input terminal and the ground terminal and configured to receive and invert an inverted boosted detection signal from the control terminal to output a boosted detection signal; and
an electrostatic discharge (ESD) transistor electrically coupled between the voltage input terminal and the ground terminal and configured to be controlled by the boosted detection signal for performing discharging on the voltage input terminal when being controlled to be turned on by the boosted detection signal;
wherein under an ordinary operation mode that a voltage at the voltage input terminal does not exceed a predetermined level, the detection signal is at a low state level, the inverted detection signal is at a high state level, the first NMOS circuit is turned on and the first PMOS circuit and the second NMOS circuit are turned off, the inverted boosted detection signal is at the high state level and the boosted detection signal is at the low state level such that the electrostatic discharge transistor is turned off; and
wherein under a discharging mode that a voltage at the voltage input terminal exceeds a predetermined level due to a reception of an electrostatic input, the detection signal is at a high state level, the inverted detection signal is at a low state level, the first NMOS circuit is turned off and the first PMOS circuit and the second NMOS circuit are turned on, the inverted boosted detection signal is at the low state level and the boosted detection signal is at the high state level such that the electrostatic discharge transistor is turned on.
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