US 12,218,126 B2
ESD protection structure, ESD protection circuit, and chip
Qian Xu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Oct. 21, 2021, as Appl. No. 17/451,670.
Application 17/451,670 is a continuation of application No. PCT/CN2021/111532, filed on Aug. 9, 2021.
Prior Publication US 2023/0040542 A1, Feb. 9, 2023
Int. Cl. H01L 27/02 (2006.01)
CPC H01L 27/0262 (2013.01) [H01L 27/0255 (2013.01); H01L 27/0292 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An electrostatic discharge protection structure, comprising:
a semiconductor substrate, comprising a first integrated region;
a first N-type well, located in the first integrated region;
a first P-type well, located in the first integrated region, and arranged adjacent to the first N-type well;
a first N-type doped portion, located in the first N-type well;
a first P-type doped portion, located in the first N-type well, and located on a side of the first N-type doped portion close to the first P-type well;
a second N-type doped portion, located in the first P-type well; and
a second P-type doped portion, located in the first P-type well, and located on a side of the second N-type doped portion away from the first N-type well, wherein
the first N-type doped portion is electrically connected to the second P-type doped portion;
wherein the semiconductor substrate further comprises a second integrated region, the first integrated region and the second integrated region are arranged at interval, and the electrostatic discharge protection structure further comprises:
a second N-type well, located in the second integrated region;
a second P-type well, located in the second integrated region, and arranged adjacent to the second N-type well;
a third N-type doped portion, located in the second N-type well;
a third P-type doped portion, located in the second N-type well, and located on a side of the third N-type doped portion close to the second P-type well;
a fourth N-type doped portion, located in the second P-type well; and
a fourth P-type doped portion, located in the second P-type well, and located on a side of the fourth N-type doped portion away from the second N-type well, wherein
the third N-type doped portion is electrically connected to the fourth P-type doped portion, and the second N-type doped portion is electrically connected to the third P-type doped portion;
wherein the electrostatic discharge protection structure further comprises:
a third P-type well, located in the first integrated region, and located on a side of the first N-type well away from the first P-type well, wherein the third P-type well is arranged adjacent to the first N-type well;
a fifth P-type doped portion, located in the first N-type well, and located on a side of the first N-type doped portion away from the first P-type doped portion;
a fifth N-type doped portion, located in the third P-type well; and
a sixth P-type doped portion, located in the third P-type well, and located on a side of the fifth N-type doped portion away from the first N-type well, wherein
the first N-type doped portion is electrically connected to the sixth P-type doped portion.