US 12,218,125 B2
Electro-static discharge protection structure and chip
Qian Xu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Apr. 7, 2022, as Appl. No. 17/658,293.
Claims priority of application No. 202110793560.7 (CN), filed on Jul. 14, 2021.
Prior Publication US 2023/0012968 A1, Jan. 19, 2023
Int. Cl. H01L 27/02 (2006.01); H02H 9/04 (2006.01)
CPC H01L 27/0259 (2013.01) [H01L 27/0255 (2013.01); H02H 9/046 (2013.01); H01L 27/0288 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An electro-static discharge protection structure, comprising:
a semiconductor substrate;
a first P-type well, located in the semiconductor substrate;
a first N-type well, located in the semiconductor substrate;
a first N-type doped portion, located in the first N-type well;
a first P-type doped portion, located in the first N-type well, and spaced apart from the first N-type doped portion;
a second N-type doped portion, located in the first P-type well;
a second P-type doped portion, located in the first P-type well, and spaced apart from the second N-type doped portion;
a third doped well, located in the semiconductor substrate;
a third P-type doped portion, located in the third doped well; and
a third N-type doped portions, located in the third doped well, and spaced apart from the third P-type doped portion,
wherein the second N-type doped portion, the second P-type doped portion and the third N-type doped portion are electrically connected; and the first N-type doped portion is electrically connected to the third P-type doped portion.