US 12,218,122 B2
Read-only memory circuit
Jacklyn Chang, Hsinchu (TW); and Kuoyuan (Peter) Hsu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 1, 2023, as Appl. No. 18/363,171.
Application 16/688,696 is a division of application No. 15/863,090, filed on Jan. 5, 2018, granted, now 10,490,544, issued on Nov. 26, 2019.
Application 15/863,090 is a division of application No. 14/610,158, filed on Jan. 30, 2015, granted, now 9,887,186, issued on Feb. 6, 2018.
Application 18/363,171 is a continuation of application No. 17/323,467, filed on May 18, 2021, granted, now 11,764,202.
Application 17/323,467 is a continuation of application No. 16/688,696, filed on Nov. 19, 2019, granted, now 11,024,621, issued on Jun. 1, 2021.
Prior Publication US 2023/0378160 A1, Nov. 23, 2023
Int. Cl. H01L 27/02 (2006.01); G06F 30/392 (2020.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 20/00 (2023.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 20/34 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
first and second read-only memory (ROM) cells aligned along a first active structure comprising a first shared source portion of the first and second ROM cells;
third and fourth ROM cells aligned along a second active structure comprising a second shared source portion of the third and fourth ROM cells;
a first bit line overlying the first and second ROM cells;
a second bit line overlying the third and fourth ROM cells;
a reference voltage line positioned between the first and second bit lines and in a same metal layer as the first and second bit lines; and
a conductive structure electrically connected to each of the first and second shared source portions and the reference voltage line,
wherein the conductive structure is positioned in a metal layer below the same metal layer.