US 12,218,121 B2
Semiconductor devices having improved layout designs, and methods of designing and fabricating the same
Jung Ho Do, Hwaseong-si (KR); and Sanghoon Baek, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jul. 12, 2021, as Appl. No. 17/373,510.
Claims priority of application No. 10-2020-0174964 (KR), filed on Dec. 15, 2020.
Prior Publication US 2022/0189944 A1, Jun. 16, 2022
Int. Cl. G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01)
CPC H01L 27/0207 (2013.01) [G06F 30/392 (2020.01); G06F 30/394 (2020.01); H01L 23/5286 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device including a first cell region, comprising:
an active pattern extending in a first direction, inside the first cell region;
a gate electrode extending in a second direction intersecting the first direction, inside the first cell region;
a source/drain contact connected to a source/drain region of the active pattern, on one side of the gate electrode; and
a first wiring pattern extending in the first direction and connected to one of the gate electrode and the source/drain contact;
wherein a part of the first wiring pattern protrudes from a boundary of the first cell region, and wherein a length of the first wiring pattern extending in the first direction is two gate pitches or less.