US 12,218,119 B2
Stacked interposer structures
Owen R. Fay, Meridian, ID (US); and Chan H. Yoo, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/931,284.
Application 17/931,284 is a continuation of application No. 16/715,242, filed on Dec. 16, 2019, granted, now 11,444,067.
Prior Publication US 2023/0005904 A1, Jan. 5, 2023
Int. Cl. H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/16 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/16146 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A stacked interposer structure, comprising:
a first interposer comprising:
a first core comprising a semiconductor material;
a first redistribution structure comprising multiple redistribution layers (RDLs) over a side of the first core, the first redistribution structure configured for operably coupling, on a surface of the first redistribution structure, to one or more memory device stack locations and to a processor device location;
cache memory at least partially within the first core adjacent the first redistribution structure under and operably coupled through the first redistribution structure to the processor device location; and
a first set of through silicon vias (TSVs) extending from the first redistribution structure through the first core to an opposite side of the first core; and
a second interposer comprising:
a second core comprising a semiconductor material;
a second redistribution structure comprising multiple redistribution layers (RDLs) over a side of the second core;
a second set of through silicon vias (TSVs) extending from the second redistribution structure through the second core to an opposite side of the second core;
the first interposer and the second interposer being oriented with the first redistribution structure and the second redistribution structure facing in a common direction; and
the first and second redistribution structures being operably coupled through only one of the first set of TSVs and the second set of TSVs.