	US 12,218,106 B2
	Backside contact to improve thermal dissipation away from semiconductor devices
Min-Feng Kao, Chiayi (TW); Dun-Nian Yaung, Taipei (TW); Hsing-Chih Lin, Tainan (TW); Jen-Cheng Liu, Hsin-Chu (TW); Yi-Shin Chu, Hsinchu (TW); Ping-Tzu Chen, Tainan (TW); and Che-Wei Chen, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 25, 2023, as Appl. No. 18/358,186.
Application 18/358,186 is a continuation of application No. 17/703,088, filed on Mar. 24, 2022, granted, now 11,756,936.
Application 17/703,088 is a continuation of application No. 16/898,613, filed on Jun. 11, 2020, granted, now 11,289,455, issued on Mar. 29, 2022.
Prior Publication US 2023/0369293 A1, Nov. 16, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01)

CPC H01L 25/0657 (2013.01) [H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05684 (2013.01); H01L 2224/08146 (2013.01); H01L 2225/06541 (2013.01)]

20 Claims

1. A three-dimensional (3D) integrated circuit (IC) stack comprising:

a first semiconductor substrate including a first integrated circuit;

a second semiconductor substrate including a second integrated circuit, the second semiconductor substrate arranged over the first semiconductor substrate; and

a first backside contact extending from a backside of the second semiconductor substrate and being thermally coupled to an interconnect structure of the first integrated circuit or the second integrated circuit; and

a through substrate via (TSV) extending through the second semiconductor substrate from the backside of the second semiconductor substrate to a frontside of the second semiconductor substrate, wherein the TSV is laterally spaced apart from the first backside contact.