US 12,218,104 B2
Method for forming chip package structure with molding layer
Wei-Yu Chen, New Taipei (TW); and An-Jhih Su, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/884,162.
Application 17/884,162 is a division of application No. 16/801,395, filed on Feb. 26, 2020, granted, now 11,469,215.
Application 15/801,846 is a division of application No. 15/208,764, filed on Jul. 13, 2016, granted, now 9,825,007, issued on Nov. 21, 2017.
Application 16/801,395 is a continuation in part of application No. 15/801,846, filed on Nov. 2, 2017, granted, now 10,734,357, issued on Aug. 4, 2020.
Claims priority of provisional application 62/894,360, filed on Aug. 30, 2019.
Prior Publication US 2022/0384213 A1, Dec. 1, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/03 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/12 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/97 (2013.01); H01L 25/03 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/19 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/24227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/97 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06582 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a chip package structure, comprising:
forming a first molding layer surrounding a first chip structure;
disposing a second chip structure over the first chip structure and the first molding layer;
forming a second molding layer surrounding the second chip structure and over the first chip structure and the first molding layer, wherein the first chip structure, the second chip structure, the first molding layer, and the second molding layer together form a first chip package unit;
providing a second chip package unit and a third chip package unit, wherein the second chip package unit is between the first chip package unit and the third chip package unit, the second chip package unit comprises a third chip structure and a fourth chip structure over the third chip structure, and the third chip package unit comprises a fifth chip structure and a sixth chip structure over the fifth chip structure;
forming a third molding layer surrounding the first molding layer, the second molding layer, the second chip package unit, and the third chip package unit, wherein the third molding layer separates the first chip package unit from the second chip package unit and separates the second chip package unit from the third chip package unit, a first bottom surface of the first molding layer and a second bottom surface of the third molding layer are substantially level with each other, and the third molding layer exposes a third bottom surface of the first chip package unit, a fourth bottom surface of the second chip package unit, and a fifth bottom surface of the third chip package unit;
forming a first insulating layer over the second chip structure, the second molding layer, the third molding layer, the second chip package unit, and the third chip package unit;
after forming the first insulating layer over the second chip structure, the second molding layer and the third molding layer, disposing a seventh chip structure over the first insulating layer, the second chip structure, the second molding layer, the third molding layer, and the second chip package unit, wherein the seventh chip structure overlaps the second chip structure and the fourth chip structure;
forming a fourth molding layer surrounding the seventh chip structure and over the first insulating layer, the second chip structure, the second molding layer and the third molding layer, wherein the first insulating layer is made of a first material, the third molding layer is made of a second material, the fourth molding layer is made of a third material, the first material is different from the second material and the third material, and the first insulating layer separates the fourth molding layer from the third molding layer and is in contact with the second chip structure and the seventh chip structure; and
cutting through the third molding layer, the first insulating layer, and the fourth molding layer, wherein a boundary between the fourth molding layer and the first insulating layer is connected to a first sidewall of the fourth molding layer.