| CPC H01L 25/0657 (2013.01) [H01L 24/32 (2013.01); H01L 23/481 (2013.01); H01L 2224/32147 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1511 (2013.01); H01L 2924/15311 (2013.01)] | 20 Claims |
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1. A semiconductor package comprising:
a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, and the first semiconductor chip including a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate;
a plurality of second semiconductor chips including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, the active surface of the second semiconductor substrate facing the inactive surface of the first semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip;
a plurality of bonding pads arranged between the first semiconductor chip and the plurality of second semiconductor chips;
a chip bonding insulating layer configured to surround the plurality of bonding pads and arranged between the first semiconductor chip and the plurality of second semiconductor chips; and
at least one supporting dummy substrate stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof,
wherein at least some of the plurality of second semiconductor chips comprise a plurality of second through electrodes penetrating at least a portion of the second semiconductor substrate,
wherein the plurality of bonding pads electrically connect the plurality of first through electrodes to the plurality of second through electrodes,
wherein a total vertical height of the at least one supporting dummy substrate is greater than respective vertical heights of the first semiconductor chip and the plurality of second semiconductor chips.
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