US 12,218,101 B2
Three-dimensional stacking semiconductor assemblies and methods of manufacturing the same
Owen R. Fay, Meridian, ID (US); Chan H. Yoo, Boise, ID (US); and Mark E. Tuttle, Meridian, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 17, 2022, as Appl. No. 17/697,141.
Application 17/697,141 is a continuation of application No. 16/440,328, filed on Jun. 13, 2019, granted, now 11,309,285.
Prior Publication US 2022/0208736 A1, Jun. 30, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/561 (2013.01); H01L 23/3171 (2013.01); H01L 23/53238 (2013.01); H01L 24/17 (2013.01); H01L 24/96 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/165 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a semiconductor substrate having an active side and a backside opposite the active side, the substrate including a metallization layer at least partially embedded in the substrate such that portions of the metallization layer remain uncovered by the substrate on both the active side and backside of the substrate,
wherein the backside of the substrate includes a divot defined by sidewalls, wherein a portion of the metallization layer is uncovered within the divot for providing an electrical connection between an external device and the metallization layer;
a dielectric layer over the semiconductor substrate, wherein portions of the dielectric layer is within the divot and on the sidewalls; and a metal bump located with the divot, protruding away from the backside, the metal bump directly contacting the metallization layer through the dielectric layer and including at least a pair of opposing peripheral surfaces that are separated from the portions of the dielectric layer on the sidewalls of the divot.