US 12,218,100 B2
Semiconductor package
Inhyo Hwang, Asan-si (KR); and Young Lyong Kim, Anyang-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 25, 2022, as Appl. No. 17/680,617.
Claims priority of application No. 10-2021-0107450 (KR), filed on Aug. 13, 2021.
Prior Publication US 2023/0047345 A1, Feb. 16, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17183 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first semiconductor chip provided on a package substrate;
an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip; and
a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip,
wherein the interconnection substrate comprises a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and
wherein the passive device is electrically connected to the second semiconductor chip.