US 12,218,098 B2
Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
Petteri Palm, Regensburg (DE); Thorsten Scharf, Regensburg (DE); and Ralf Wombacher, Burglengenfeld (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Apr. 18, 2022, as Appl. No. 17/722,929.
Application 15/632,680 is a division of application No. 14/613,446, filed on Feb. 4, 2015, abandoned.
Application 17/722,929 is a continuation of application No. 16/904,052, filed on Jun. 17, 2020, granted, now 11,309,277.
Application 16/904,052 is a continuation of application No. 16/107,264, filed on Aug. 21, 2018, granted, now 10,734,351, issued on Aug. 4, 2020.
Application 16/107,264 is a continuation of application No. 15/632,680, filed on Jun. 26, 2017, granted, now 10,056,348, issued on Aug. 21, 2018.
Claims priority of application No. 10 2014 101 366.2 (DE), filed on Feb. 4, 2014.
Prior Publication US 2022/0238481 A1, Jul. 28, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/78 (2006.01); H01L 23/055 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/498 (2006.01)
CPC H01L 24/82 (2013.01) [H01L 21/4853 (2013.01); H01L 21/486 (2013.01); H01L 21/78 (2013.01); H01L 23/055 (2013.01); H01L 23/481 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/25 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/49816 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/82039 (2013.01); H01L 2224/8285 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83132 (2013.01); H01L 2224/83191 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92144 (2013.01); H01L 2224/97 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic module, comprising:
an electrically conductive first substrate;
a first dielectric layer on the first substrate;
an electronic chip, which is mounted with a first main surface directly or on a section of the first dielectric layer;
an electrically conductive second substrate over a second main surface of the at least one electronic chip;
a second dielectric layer on the second substrate, wherein the electronic chip is mounted with its second main surface directly on a section of the second dielectric layer;
an electrical contacting for electrically contacting a first pad of the at least one electronic chip on the first main surface of the at least one electronic chip through the first dielectric layer;
a further electrical contacting for electrically contacting a second pad of the at least one electronic chip on the second main surface of the at least one electronic chip through a plurality of clearance boles penetrating the second dielectric layer;
wherein the first dielectric layer on the first substrate extends across an area, which exceeds the first main surface, and
wherein the first dielectric layer is formed by a first partial layer on the first substrate and a separate second partial layer on the first partial layer where the first partial layer is between the first substrate and the second partial layer, the first partial layer and the second partial layer comprising different material compositions.