US 12,218,096 B2
Semiconductor package and method of forming the same
Yeongkwon Ko, Hwaseong-si (KR); Unbyoung Kang, Hwaseong-si (KR); Soyeon Kwon, Cheonan-si (KR); Yoonsung Kim, Seoul (KR); and Teakhoon Lee, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 29, 2022, as Appl. No. 17/707,007.
Claims priority of application No. 10-2021-0107287 (KR), filed on Aug. 13, 2021.
Prior Publication US 2023/0048729 A1, Feb. 16, 2023
Int. Cl. H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 25/18 (2023.01)
CPC H01L 24/26 (2013.01) [H01L 23/544 (2013.01); H01L 24/32 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05562 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/26145 (2013.01); H01L 2224/26175 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/06513 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a base;
a plurality of semiconductor chips stacked on the base in a vertical direction;
connection patterns electrically connecting the plurality of semiconductor chips; and
adhesive material layers filling at least a space between the plurality of semiconductor chips and covering side surfaces of the connection patterns,
wherein the plurality of semiconductor chips include a first semiconductor chip and a second semiconductor chip sequentially stacked in the vertical direction,
the connection patterns include a first connection pattern disposed between the first semiconductor chip and the second semiconductor chip and electrically connecting the first semiconductor chip and the second semiconductor chip, and
the first semiconductor chip includes:
a first semiconductor substrate having a first front side and a first back side opposing each other, the first semiconductor substrate having a first chip area and a first dummy area surrounding the first chip area;
a first front structure disposed below the first front side of the first semiconductor substrate, and including a first internal circuit, a first guard pattern, a first internal connection pattern, and a first front insulating structure;
on the first back side of the first semiconductor substrate, a first rear protective layer overlapping the first chip area and the first dummy area, and a first rear protrusion pattern disposed on the first rear protective layer and overlapping the first dummy area;
a first through-electrode structure penetrating through the first chip area of the first semiconductor substrate and the first rear protective layer, and electrically connected to the first internal connection pattern in the first front structure; and
a first rear pad electrically connected to the first through-electrode structure, on the first rear protective layer and the first through-electrode structure, and spaced apart from the first rear protrusion pattern,
wherein the first internal circuit and the first internal connection pattern are disposed below the first chip area of the first semiconductor substrate, and
the first guard pattern is disposed below the first chip area of the first semiconductor substrate adjacent to the first dummy area.