US 12,218,095 B2
Chip package structure having molding layer
Shin-Puu Jeng, Hsinchu (TW); Shuo-Mao Chen, New Taipei (TW); and Feng-Cheng Hsu, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,196.
Application 16/403,897 is a division of application No. 15/708,456, filed on Sep. 19, 2017, granted, now 10,283,474, issued on May 7, 2019.
Application 18/361,196 is a continuation of application No. 17/554,475, filed on Dec. 17, 2021, granted, now 11,791,301.
Application 17/554,475 is a continuation of application No. 16/750,071, filed on Jan. 23, 2020, granted, now 11,239,194, issued on Feb. 1, 2022.
Application 16/750,071 is a continuation of application No. 16/403,897, filed on May 6, 2019, granted, now 10,546,830, issued on Jan. 28, 2020.
Claims priority of provisional application 62/527,161, filed on Jun. 30, 2017.
Prior Publication US 2024/0006367 A1, Jan. 4, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 21/78 (2006.01); H01L 23/29 (2006.01)
CPC H01L 24/25 (2013.01) [H01L 21/56 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/24 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/29 (2013.01); H01L 23/3114 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13184 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/215 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81193 (2013.01); H01L 2224/81801 (2013.01); H01L 2225/1047 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/1304 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A chip package structure, comprising:
a first redistribution structure having a first surface and a second surface opposite to the first surface;
a first chip over the first surface;
a first conductive pillar over the first surface and adjacent to the first chip;
a second chip over the second surface;
a second conductive pillar over the second surface and adjacent to the second chip;
a first molding layer over the first surface and surrounding the first chip, wherein the first conductive pillar passes through the first molding layer, a first portion of the first molding layer covers a first bottom surface of the first chip, and the first bottom surface faces away from the first redistribution structure;
a second molding layer over the second surface and surrounding the second chip, wherein the second conductive pillar passes through the second molding layer, a second portion of the second molding layer covers a first top surface of the second chip, the first top surface faces away from the first redistribution structure, and
the first chip, the first redistribution structure, and the second chip are between the first portion of the first molding layer and the second portion of the second molding layer;
a second redistribution structure over the second chip;
a buffer layer between the second redistribution structure and the second chip;
a third chip over the second redistribution structure, wherein the second redistribution structure is between the third chip and the buffer layer; and
a conductive bump passing through the buffer layer and connected between the second conductive pillar and the second redistribution structure, wherein a width of the conductive bump continuously decreases from the second redistribution structure to the second conductive pillar.