US 12,218,093 B2
Semiconductor die connection system and method
Ming-Fa Chen, Taichung (TW); Chen-Hua Yu, Hsinchu (TW); and Sen-Bor Jan, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 12, 2023, as Appl. No. 18/332,990.
Application 17/837,492 is a division of application No. 16/715,600, filed on Dec. 16, 2019, granted, now 11,387,205, issued on Jul. 12, 2022.
Application 18/332,990 is a continuation of application No. 17/837,492, filed on Jun. 10, 2022, granted, now 11,855,029.
Application 16/715,600 is a continuation of application No. 15/375,690, filed on Dec. 12, 2016, granted, now 10,510,701, issued on Dec. 17, 2019.
Application 15/375,690 is a continuation of application No. 14/875,499, filed on Oct. 5, 2015, granted, now 9,520,340, issued on Dec. 13, 2016.
Application 14/875,499 is a continuation of application No. 13/947,953, filed on Jul. 22, 2013, granted, now 9,153,540, issued on Oct. 6, 2015.
Application 13/947,953 is a continuation of application No. 13/346,398, filed on Jan. 9, 2012, granted, now 8,518,796, issued on Aug. 27, 2013.
Prior Publication US 2023/0326895 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 21/784 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 24/16 (2013.01) [H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/76898 (2013.01); H01L 21/78 (2013.01); H01L 21/784 (2013.01); H01L 23/3185 (2013.01); H01L 23/481 (2013.01); H01L 23/5384 (2013.01); H01L 24/17 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/566 (2013.01); H01L 23/3114 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/14181 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/181 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first die with a first width over a second die with a second width, wherein the second width is larger than the first width;
a through via in a substrate of the first die, wherein the through via has a top surface coplanar with a top surface of the substrate of the first die, wherein the through via has a bottom surface within the first die;
an underfill material between the first die and the second die; and
an encapsulant extending along a surface of the underfill material and a surface of the second die.