US 12,218,092 B2
Semiconductor package and method of manufacturing semiconductor package
Moonyong Jang, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 9, 2022, as Appl. No. 17/690,270.
Claims priority of application No. 10-2021-0101795 (KR), filed on Aug. 3, 2021.
Prior Publication US 2023/0039094 A1, Feb. 9, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/16 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/13 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 25/0657 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 2224/13007 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13541 (2013.01); H01L 2224/13553 (2013.01); H01L 2224/1357 (2013.01); H01L 2224/1403 (2013.01); H01L 2224/16014 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81203 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1438 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate including wiring patterns provided respectively in a plurality of insulation layers, the package substrate having insertion holes extending from an upper surface of the package substrate in a thickness direction of the package substrate to expose portions of the wiring patterns in different insulation layers;
a semiconductor chip disposed on the package substrate, the semiconductor chip having a first surface on which chip pads are formed;
a plurality of connection pins provided on the chip pads, respectively, the plurality of connection pins extending through corresponding ones of the insertion holes and electrically connecting to the portions of the wiring patterns, respectively, that are exposed by the insertion holes; and
a molding member provided on the package substrate to cover the semiconductor chip,
wherein heights of the plurality of connection pins from the first surface of the semiconductor chip are greater than depths of the corresponding ones of the insertion holes from the upper surface of the package substrate such that the plurality of connection pins physically contact the portions of the wiring patterns that are exposed by the corresponding ones of the insertion holes,
wherein each of the plurality of connection pins includes a connection pillar provided on the respective chip pad and extending from the first surface of the semiconductor chip and a metal bonding layer provided to cover an entire outer surface of the connection pillar, and
wherein the metal bonding layers of the plurality of connection pins physically contact and form a thermo-compression bond with the portions of the wiring patterns, respectively, that are exposed by the insertion holes.