US 12,218,089 B2
Packaged semiconductor device and method of forming thereof
Chen-Hua Yu, Hsinchu (TW); Kuo-Chung Yee, Taoyuan (TW); and Chih-Hang Tung, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jan. 12, 2023, as Appl. No. 18/153,847.
Application 18/153,847 is a continuation of application No. 17/232,528, filed on Apr. 16, 2021, granted, now 11,581,281.
Claims priority of provisional application 63/044,608, filed on Jun. 26, 2020.
Prior Publication US 2023/0170320 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/08 (2013.01) [H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first die, the first die comprising:
a first substrate;
a first interconnect structure on a first side of the first substrate; and
a first device layer on a second side of the first substrate;
a second die on the first die, the second die comprising:
a second substrate;
a second interconnect structure on a first side of the second substrate, the second interconnect structure comprising a first line, the first line having a first thickness; and
a power distribution network (PDN) layer on the second interconnect structure, a conductive line of the PDN layer having a second thickness, the second thickness being greater than the first thickness; and
a third die on the second die, the third die comprising:
a third substrate; and
a second device layer on a first side of the third substrate.