US 12,218,082 B2
Package structure
Kai-Ming Chiang, Hsinchu (TW); Chao-wei Li, Hsinchu (TW); Wei-Lun Tsai, Hsinchu (TW); Chia-Min Lin, Hsinchu (TW); Yi-Da Tsai, Chiayi Country (TW); Sheng-Feng Weng, Taichung (TW); Yu-Hao Chen, HsinChu (TW); Sheng-Hsiang Chiu, Tainan (TW); Chih-Wei Lin, Hsinchu County (TW); and Ching-Hua Hsieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 9, 2023, as Appl. No. 18/506,111.
Application 18/506,111 is a continuation of application No. 17/389,313, filed on Jul. 29, 2021, granted, now 11,855,006.
Prior Publication US 2024/0071954 A1, Feb. 29, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2221/68372 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure, comprising:
a first semiconductor die comprising conductive terminals;
second semiconductor dies stacked over the first semiconductor die, the conductive terminals being spaced apart from the second semiconductor die by the first semiconductor die;
an insulating encapsulation disposed on the first semiconductor die to laterally encapsulate the second semiconductor die, sidewalls of the insulating encapsulation being substantially aligned with sidewalls of the first semiconductor die; and
a buffer cap encapsulating the conductive terminals, wherein the buffer cap covers the sidewalls of the first semiconductor die and the sidewalls of the insulating encapsulation, wherein a maximum height of the buffer cap substantially equals to a sum of a first height of the first semiconductor die, a second height of the second semiconductor dies, and a third height of the conductive terminals.