US 12,218,078 B2
Semiconductor memory device and manufacturing method of the semiconductor memory device
Jun Hyuk Park, Icheon-si (KR); Kyung Min Park, Icheon-si (KR); Sung Gon Jin, Icheon-si (KR); and Dong Won Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 5, 2022, as Appl. No. 17/713,869.
Claims priority of application No. 10-2021-0143985 (KR), filed on Oct. 26, 2021.
Prior Publication US 2023/0129734 A1, Apr. 27, 2023
Int. Cl. H01L 23/00 (2006.01); H10B 43/27 (2023.01); H10B 51/20 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 23/562 (2013.01) [H10B 43/27 (2023.02); H10B 51/20 (2023.02); H10B 61/22 (2023.02); H10B 63/34 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a lower stack structure including a lower scribe region and a lower chip region;
forming a lower hole penetrating the lower scribe region of the lower stack structure;
forming, in the lower hole, a measurement pillar including a buried layer disposed at a lower portion of the lower hole, and a reflective metal layer and an etch stop layer, which are disposed at an upper portion of the lower hole;
forming an upper stack structure on the lower stack structure to cover the measurement pillar; and
forming an upper hole overlapping with the measurement pillar, the upper hole penetrating the upper stack structure,
wherein a hardness of the buried layer is less than hardnesses of the reflective metal layer and the etch stop layer, and
wherein the reflective metal layer is formed of a material having an atomic number greater than an atomic number of the etch stop layer.