US 12,218,075 B2
Package structure
Cheng-Yuan Kung, Kaohsiung (TW); Hsu-Chiang Shih, Kaohsiung (TW); Hung-Yi Lin, Kaohsiung (TW); and Chien-Mei Huang, Kaohsiung (TW)
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung (TW)
Filed by Advanced Semiconductor Engineering, Inc., Kaohsiung (TW)
Filed on Dec. 30, 2021, as Appl. No. 17/566,575.
Prior Publication US 2023/0215816 A1, Jul. 6, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/1511 (2013.01); H01L 2924/3512 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A package structure, comprising:
an encapsulant;
a patterned circuit structure disposed on the encapsulant, and including a pad;
at least one electronic component disposed on the patterned circuit structure, and including a bump electrically connected to the pad; and
a shrinkage modifier encapsulated in the encapsulant and configured to reduce a relative displacement between the bump and the pad along a horizontal direction in an environment of temperature variation, wherein a coefficient of thermal expansion of the shrinkage modifier is less than a coefficient of thermal expansion of the patterned circuit structure and a coefficient of thermal expansion of the encapsulant.