US 12,218,074 B2
DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure
Harry-Hak-Lay Chuang, Zhubei (TW); Tien-Wei Chiang, Taipei (TW); Kuo-An Liu, Hsinchu (TW); and Chia-Hsiang Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 9, 2023, as Appl. No. 18/332,047.
Application 17/393,651 is a division of application No. 16/381,410, filed on Apr. 11, 2019, granted, now 11,088,083, issued on Aug. 10, 2021.
Application 18/332,047 is a continuation of application No. 17/393,651, filed on Aug. 4, 2021, granted, now 11,715,702.
Claims priority of provisional application 62/692,238, filed on Jun. 29, 2018.
Prior Publication US 2023/0317629 A1, Oct. 5, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/552 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H01L 23/552 (2013.01) [H01L 23/49555 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49176 (2013.01); H01L 2924/1443 (2013.01); H01L 2924/3025 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a chip comprising a semiconductor device; and
a shielding structure abutting the chip, wherein the shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip, wherein the first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers, wherein the first dielectric layer is disposed between the two or more metal layers.