US 12,218,071 B2
Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers
Srinivas V. Pietambaram, Gilbert, AZ (US); Sri Ranga Sai Boyapati, Chandler, AZ (US); Robert A. May, Chandler, AZ (US); Kristof Darmawikarta, Chandler, AZ (US); Javier Soto Gonzalez, Chandler, AZ (US); and Kwangmo Lim, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 12, 2023, as Appl. No. 18/208,785.
Application 18/208,785 is a continuation of application No. 17/374,886, filed on Jul. 13, 2021, granted, now 11,735,531.
Application 17/374,886 is a continuation of application No. 16/326,679, granted, now 11,101,222, issued on Aug. 24, 2021, previously published as PCT/US2016/054559, filed on Sep. 29, 2016.
Prior Publication US 2023/0326866 A1, Oct. 12, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 23/00 (2013.01); H01L 24/06 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/18162 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A package, comprising:
a die having a plurality of die pads;
a molding layer laterally surrounding the die and the plurality of die pads, the molding layer having an uppermost surface at a same level as an uppermost surface of the plurality of die pads;
a plurality of conductive vias, wherein individual ones of the plurality of conductive vias are on a corresponding one of the plurality of die pads, each of the plurality of conductive vias having an uppermost surface, wherein the uppermost surface of each of the conductive vias is vertically overlapping with the corresponding one of the die pads; and
a plurality of conductive traces on the uppermost surface of the molding layer over the die, the plurality of conductive traces having an uppermost surface below the uppermost surface of each of the plurality of conductive vias.