US 12,218,070 B2
Semiconductor package and method of fabricating the same
Hae-Jung Yu, Seoul (KR); and Kyung Suk Oh, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 12, 2023, as Appl. No. 18/133,656.
Application 18/133,656 is a continuation of application No. 17/106,273, filed on Nov. 30, 2020, granted, now 11,637,070.
Application 17/106,273 is a continuation of application No. 16/161,460, filed on Oct. 16, 2018, granted, now 10,854,551, issued on Dec. 1, 2020.
Claims priority of application No. 10-2018-0014810 (KR), filed on Feb. 6, 2018.
Prior Publication US 2023/0245975 A1, Aug. 3, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5386 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 23/13 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24146 (2013.01); H01L 2224/82005 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/1431 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including first redistribution pads on the first surface and first vias below the first redistribution pads;
a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including an active surface facing the redistribution layer, a first side surface, and a second side surface opposite the first side surface;
a wiring substrate on the second surface of the redistribution layer and surrounding the semiconductor chip, the wiring substrate including base layers and conductive structures in the base layers, the conductive structures being spaced apart from the semiconductor chip, and each of the conductive structures including a conductive pad at one end;
a molding member encapsulating the semiconductor chip, contacting side surfaces of the wiring substrate, and having openings exposing the conductive pads; and
external connection terminals on and contacting the conductive pads of the conductive structures,
wherein the conductive pads are arranged according to a first separation distance, and the first redistribution pads are arranged according to a second separation distance,
wherein the second separation distance is smaller than the first separation distance,
wherein the first separation distance is defined as a distance between a pair of adjacent ones of the conductive pads positioned closer to the second side surface than to the first side surface of the semiconductor chip,
wherein upper surfaces of the first vias are at the same vertical level as the first surface of the redistribution layer, and
wherein each of the first redistribution pads contacts a corresponding one of the first vias.