US 12,218,066 B2
Monolithic formation of a set of interconnects below active devices
Daniel Chanemougame, Niskayuna, NY (US); Lars Liebmann, Mechanicsville, NY (US); and Jeffrey Smith, Clifton Park, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Aug. 30, 2023, as Appl. No. 18/458,591.
Application 18/458,591 is a division of application No. 17/306,331, filed on May 3, 2021, granted, now 11,791,271.
Claims priority of provisional application 63/085,578, filed on Sep. 30, 2020.
Prior Publication US 2023/0411298 A1, Dec. 21, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 27/092 (2006.01)
CPC H01L 23/5383 (2013.01) [H01L 21/4885 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabrication, the method comprising:
providing a substrate, the substrate comprising bulk semiconductor material;
forming an opening in the bulk semiconductor material patterned for a first wiring structure;
filling the opening in the bulk semiconductor material with a metal such that the first wiring structure is formed at least partially within the bulk semiconductor material;
epitaxially growing active semiconductor material over the first wiring structure so that the bulk semiconductor material and the active semiconductor material are in direct contact with each other, wherein the bulk semiconductor material and the active semiconductor material together form a monocrystalline structure;
forming one or more active devices in the active semiconductor material over the first wiring structure; and
forming a second wiring structure over the one or more active devices.