US 12,218,064 B2
Molded silicon interconnects in bridges for integrated-circuit packages
Bok Eng Cheah, Bukit Gambir (MY); Jenny Shio Yin Ong, Bayan Lepas (MY); Seok Ling Lim, Kulim (MY); Jackson Chung Peng Kong, Tanjung Tokong (MY); and Kooi Chi Ooi, Glugor (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 17/631,254
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Jun. 26, 2020, PCT No. PCT/US2020/039891
§ 371(c)(1), (2) Date Jan. 28, 2022,
PCT Pub. No. WO2021/040877, PCT Pub. Date Mar. 4, 2021.
Claims priority of application No. 2019005034 (MY), filed on Aug. 30, 2019.
Prior Publication US 2022/0302033 A1, Sep. 22, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/5381 (2013.01) [H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 25/16 (2013.01); H01L 2224/16227 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated-circuit (IC) package structure, comprising:
a silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the silicon interconnect bridge shares the die side;
a passive device in the molding-mass frame, wherein the silicon interconnect bridge and the passive device occupy at least some of the same vertical space encompassed by the molding-mass frame; and
a redistribution layer on the die side, wherein the redistribution layer is coupled to the passive device and to a through-silicon via in the silicon interconnect bridge, wherein the through-silicon via is communicatively coupled to the package side, wherein the redistribution layer is coupled at the die side to a first IC die by a first electrical bump and to a second IC die by a second electrical bump, and wherein communication between the first IC die and the second IC die is by the through-silicon via in the silicon interconnect bridge.