US 12,218,062 B2
Method of fabricating a semiconductor memory device including an extension gate cutting region
Jun Hyoung Kim, Seoul (KR); Young-Jin Kwon, Suwon-si (KR); and Geun Won Lim, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 20, 2023, as Appl. No. 18/514,716.
Application 18/514,716 is a continuation of application No. 17/018,400, filed on Sep. 11, 2020, granted, now 11,862,566.
Claims priority of application No. 10-2020-0002422 (KR), filed on Jan. 8, 2020.
Prior Publication US 2024/0088045 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/535 (2006.01); H01L 21/768 (2006.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H10B 43/27 (2023.02); H10B 43/40 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor memory device, comprising:
providing a substrate including a cell array region and an extension region, which are arranged along a first direction, the extension region including contact regions and through regions, which are alternately arranged along the first direction;
forming a mold structure including first insulating patterns and second insulating patterns, which are alternately stacked on the substrate;
forming a channel structure through the mold structure of the cell array region to intersect the first insulating patterns and the second insulating patterns;
forming an extension gate cutting region extending in the first direction to cut the mold structure, in the mold structure of the contact regions; and
selectively removing the second insulating patterns in the contact regions, using the extension gate cutting region, so that the second insulating patterns in the through regions remain.