US 12,218,061 B2
Driving connection structures of memory devices
Ya-Chun Tsai, Hsinchu (TW)
Assigned to Macronix International Co., Ltd., Hsinchu (TW)
Filed by Macronix International Co., Ltd., Hsinchu (TW)
Filed on Jan. 12, 2022, as Appl. No. 17/574,170.
Prior Publication US 2023/0223343 A1, Jul. 13, 2023
Int. Cl. H01L 23/535 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first array structure of memory cells comprising first conductive layers;
a second array structure of memory cells comprising second conductive layers;
a connection structure arranged between the first array structure and the second array structure along a first direction; and
a circuit arranged adjacent to the connection structure,
wherein the connection structure comprises:
a first connection area through which the first conductive layers are electrically connected to the circuit,
a first stepped structure configured to individually expose the first conductive layers,
a second stepped structure configured to individually expose the second conductive layers, and
a second connection area through which the second conductive layers are connected to the circuit,
wherein the first stepped structure and the second stepped structure are arranged between the first connection area and the second connection area along a second direction perpendicular to the first direction,
wherein the first conductive layers of the first array structure are stacked along a third direction perpendicular to the first direction and the second direction, and the second conductive layers of the second array structure are stacked along the third direction,
wherein the first array structure, the first connection area, and the first stepped structure are separated from the second array structure, the second connection area, and the second stepped structure by a conductive slit structure, and
wherein the conductive slit structure comprises:
a first slit portion between the first stepped structure and the second stepped structure along the second direction, the first slit portion extending along the first direction and the third direction,
a second slit portion between the first array structure and the second connection area along the first direction, the second slit portion extending along the second direction and the third direction, and
a third slit portion between the first connection area and the second array structure along the first direction, the third slit portion extending along the second direction and the third direction.