US 12,218,060 B2
Integrated chip with graphene based interconnect
Shin-Yi Yang, New Taipei (TW); Meng-Pei Lu, Hsinchu (TW); Chin-Lung Chung, Hsin-Chu (TW); Ming-Han Lee, Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 5, 2021, as Appl. No. 17/308,361.
Prior Publication US 2022/0359413 A1, Nov. 10, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/53276 (2013.01) [H01L 21/31053 (2013.01); H01L 21/7682 (2013.01); H01L 21/76834 (2013.01); H01L 21/76877 (2013.01); H01L 21/76886 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, the method comprising:
forming a metal interconnect within a first dielectric layer over a substrate;
depositing a stack comprising a plurality of graphene layers over the substrate, wherein a first graphene layer of the plurality of graphene layers is deposited directly on the metal interconnect and the first dielectric layer;
patterning the stack to form a first stack segment and a second stack segment that are laterally separated by a cavity;
intercalating the plurality of graphene layers with one or more metals to form a first wire and a second wire from the first stack segment and the second stack segment, respectively;
depositing a second dielectric layer covering the first wire, the second wire, and the cavity, wherein a portion of the cavity remains unfilled after depositing the second dielectric layer; and
removing the second dielectric layer from over the first and second wires to define a dielectric cap that seals the cavity.