US 12,218,059 B2
Stacked IC structure with orthogonal interconnect layers
Ilyas Mohammed, Santa Clara, CA (US); Steven L. Teig, Menlo Park, CA (US); and Javier A. DeLaCruz, San Jose, CA (US)
Assigned to Adeia Semiconductor Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Inc., San Jose, CA (US)
Filed on Dec. 28, 2023, as Appl. No. 18/399,485.
Application 18/399,485 is a continuation of application No. 17/201,732, filed on Mar. 15, 2021, granted, now 11,881,454.
Application 17/201,732 is a continuation of application No. 16/806,934, filed on Mar. 2, 2020, granted, now 10,950,547, issued on Mar. 16, 2021.
Application 16/806,934 is a continuation of application No. 15/976,809, filed on May 10, 2018, granted, now 10,580,735, issued on Mar. 3, 2020.
Application 15/976,809 is a continuation in part of application No. 15/725,030, filed on Oct. 4, 2017, granted, now 10,522,352, issued on Dec. 31, 2019.
Claims priority of provisional application 62/619,910, filed on Jan. 21, 2018.
Claims priority of provisional application 62/575,184, filed on Oct. 20, 2017.
Claims priority of provisional application 62/575,240, filed on Oct. 20, 2017.
Claims priority of provisional application 62/575,259, filed on Oct. 20, 2017.
Claims priority of provisional application 62/405,833, filed on Oct. 7, 2016.
Prior Publication US 2024/0234320 A1, Jul. 11, 2024
Int. Cl. H01L 23/528 (2006.01); H01L 21/822 (2006.01); H01L 23/00 (2006.01); H01L 23/50 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01)
CPC H01L 23/5286 (2013.01) [H01L 21/8221 (2013.01); H01L 23/50 (2013.01); H01L 23/5225 (2013.01); H01L 24/26 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/15311 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A stacked integrated circuit (IC) device comprising first and second IC dies directly hybrid bonded to each other by metal-to-metal bonding and oxide-to-oxide bonding, the first IC die having power interconnect lines formed on a rear surface thereof, wherein active circuit components of one or both of the first and second IC dies are electrically connected to the power interconnect lines by through silicon vias (TSVs) formed within the first IC die.