US 12,218,056 B2
Component inter-digitated vias and leads
Christopher Kinney, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 11, 2020, as Appl. No. 17/018,812.
Application 17/018,812 is a continuation of application No. 16/280,570, filed on Feb. 20, 2019, granted, now 10,784,199.
Prior Publication US 2020/0411437 A1, Dec. 31, 2020
Int. Cl. H01L 23/528 (2006.01); G11C 5/06 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/5286 (2013.01) [G11C 5/06 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of reducing inductance on an integrated circuit package, the method comprising:
configuring the integrated circuit package to support a plurality of electrical contacts that comprise a set of power leads and a set of ground leads, the set of power leads comprising a first power lead and a second power lead, and the set of ground leads including at least a ground lead; and
arranging the plurality of electrical contacts upon the integrated circuit package in an alternating arrangement of power leads and ground leads to form an inter-digitated arrangement that comprise a first gap between the first power lead and the second power lead, and a second gap between the first power lead and the ground lead, the first gap being greater than the second gap.