| CPC H01L 23/528 (2013.01) [H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 23/5329 (2013.01); H01L 27/0886 (2013.01); H01L 29/7848 (2013.01)] | 20 Claims |
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1. A method of fabricating an integrated circuit structure, the method comprising:
forming a plurality of backbone features above a semiconductor substrate, a semiconductor layer, or a stack of semiconductor layers;
forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features;
forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features;
subsequent to forming the second set of spacers, removing the plurality of backbone features;
subsequent to removing the plurality of backbone features, forming a third set of spacers along sidewalls of each of the first set of spacers, the third set of spacers having the second material composition;
forming a final feature in each opening between adjacent pairs of spacers of the third set of spacers;
planarizing the first set of spacers, the second set of spacers, the third set of spacers, and the final features to form a target foundation layer; and
using the target foundation layer to form a plurality of fins or three-dimensional bodies in the semiconductor substrate, the semiconductor layer, or the stack of semiconductor layers.
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