US 12,218,051 B2
Method of manufacturing a semiconductor device including a plurality of circuit components and array of conductive contacts
Cheng-Yuan Li, Kaohsiung (TW); Kuo-Cheng Lee, Tainan (TW); Yun-Wei Cheng, Taipei (TW); and Yen-Liang Lin, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/869,196.
Application 17/869,196 is a division of application No. 16/201,925, filed on Nov. 27, 2018, granted, now 12,068,246.
Application 16/201,925 is a continuation in part of application No. 15/965,116, filed on Apr. 27, 2018, granted, now 11,791,299.
Claims priority of provisional application 62/592,701, filed on Nov. 30, 2017.
Prior Publication US 2022/0359370 A1, Nov. 10, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/544 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 23/5226 (2013.01); H01L 23/544 (2013.01); H01L 24/09 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02373 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of integrated circuit components over a first wafer, the plurality of integrated circuit components comprising:
a first integrated circuit component surrounded by a first seal ring;
a second integrated circuit component surrounded by a second seal ring adjacent to the first integrated circuit component; and
a scribe region between the first integrated circuit component and the second integrated circuit component;
a first array of conductive contacts along a first side of the first integrated circuit component, the first array comprising a first set of rows and a first set of columns, the first array having a first longitudinal axis extending in a first direction;
a second array of conductive contacts along a second side of the first integrated circuit component, the second array comprising a second set of rows and a second set of columns, the second array having a second longitudinal axis extending in a second direction perpendicular to the first direction;
a third array of conductive contacts along a third side of the first integrated circuit component opposite the first side, the third array of conductive contacts having a third longitudinal axis extending in the first direction;
a fourth array of conductive contacts along a fourth side of the first integrated circuit component opposite the second side, the fourth array of conductive contacts having a fourth longitudinal axis extending in the second direction, wherein each of the conductive contacts are located within one of the first array, the second array, the third array, and the fourth array, and wherein each of the first array and the third array extend no farther than one-half of the length of the first integrated circuit component in the first direction and wherein each of the second array and the fourth array extend no farther than one-half of the width of the first integrated circuit component in the second direction;
bonding the first array, the second array, the third array, and the fourth array to a second wafer; and
dicing the first integrated circuit component from the second integrated circuit component along the scribe region.