US 12,218,047 B2
Memory devices and methods of manufacturing thereof
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); Yi-Hsun Chiu, Zhubei (TW); and Yih Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 20, 2023, as Appl. No. 18/514,796.
Application 18/514,796 is a continuation of application No. 18/157,418, filed on Jan. 20, 2023, granted, now 11,856,762.
Application 18/157,418 is a continuation of application No. 16/788,245, filed on Feb. 11, 2020, granted, now 11,563,015, issued on Jan. 24, 2023.
Prior Publication US 2024/0090209 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/525 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); H10B 20/25 (2023.01)
CPC H01L 23/5252 (2013.01) [G11C 17/16 (2013.01); G11C 17/18 (2013.01); H10B 20/25 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a programming transistor of an anti-fuse memory cell comprising one or more first semiconductor nanostructures vertically spaced apart from one another, each of the one or more first semiconductor nanostructures having a first width along a first lateral direction;
a reading transistor of the anti-fuse memory cell comprising one or more second semiconductor nanostructures vertically spaced apart from one another, each of the one or more second semiconductor nanostructures having a second width different from the first width along the second direction;
a first gate metal wrapping around each of the one or more first semiconductor nanostructures with a first gate dielectric disposed therein; and
a second gate metal wrapping around each of the one or more second semiconductor nanostructures with a second gate dielectric disposed therein.