| CPC H01L 23/5226 (2013.01) [H01L 23/5283 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
transistors on a substrate;
a first interlayer insulating layer on the transistors;
a first lower interconnection line, a second lower interconnection line, and a third lower interconnection line that are provided in an upper portion of the first interlayer insulating layer;
a first dielectric layer being selectively on a top surface of the first interlayer insulating layer between the first and second lower interconnection lines;
a second dielectric layer being selectively on a top surface of the first interlayer insulating layer between the second and third lower interconnection lines;
an etch stop layer on the first, second and third lower interconnection lines and the first and second dielectric layers;
a second interlayer insulating layer on the etch stop layer; and
an upper interconnection line in the second interlayer insulating layer,
wherein the upper interconnection line includes
a first contact portion, a second contact portion and a third contact portion that are connected to the first, second and third lower interconnection lines, respectively, and
a first connecting portion between the first and second contact portions and a second connecting portion between the second and third contact portions, and
wherein a level of a bottom surface of the first connecting portion is different from a level of a bottom surface of the second connecting portion.
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