US 12,218,041 B2
Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods
Jihong Choi, San Diego, CA (US); Giridhar Nallapati, San Diego, CA (US); William Stone, San Diego, CA (US); Jianwen Xu, San Diego, CA (US); Jonghae Kim, San Diego, CA (US); Periannan Chidambaram, San Diego, CA (US); and Ahmer Syed, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 22, 2021, as Appl. No. 17/237,828.
Prior Publication US 2022/0344250 A1, Oct. 27, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 28/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package, comprising:
a package substrate comprising a plurality of package substrate interconnects;
an IC chip comprising a plurality of die interconnects;
a redistribution layer (RDL) substrate disposed between the package substrate and the IC chip, the RDL substrate comprising:
a first RDL layer comprising one or more first RDL interconnects each coupled to a first die interconnect among the plurality of die interconnects; and
a second RDL layer comprising one or more second RDL interconnects each coupled to a package substrate interconnect of the plurality of package substrate interconnects;
a dielectric layer disposed between the first RDL layer and the second RDL layer; and
a capacitor package embedded in the dielectric layer, the capacitor package comprising a capacitor;
the dielectric layer comprising:
one or more first vias each coupled to a first RDL interconnect of the one or more first RDL interconnects; and
one or more second vias that extend through the dielectric layer and are disposed through the capacitor package and each coupled to a first RDL interconnect of the one or more first RDL interconnects, and each coupled to a second RDL interconnect of the one or more second RDL interconnects; and
a molding on the IC chip, the RDL substrate, and the package substrate.