US 12,218,040 B2
Nested interposer with through-silicon via bridge die
Srinivas V. Pietambaram, Chandler, AZ (US); Debendra Mallik, Chandler, AZ (US); Kristof Darmawikarta, Chandler, AZ (US); Ravindranath V. Mahajan, Chandler, AZ (US); and Rahul N. Manepalli, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 26, 2021, as Appl. No. 17/186,289.
Prior Publication US 2022/0278032 A1, Sep. 1, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 23/49894 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 2224/16227 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
an interposer, wherein the interposer comprises:
an interposer substrate;
a cavity that passes into but not through the interposer substrate;
a through interposer via (TIV) within the interposer substrate;
an interposer pad electrically coupled to the TIV; and
a first backside pad coupled to the TIV;
a nested component in the cavity, wherein the nested component comprises a component pad coupled to a through-component via;
a core via beneath the nested component, the core via extending from the nested component through the interposer substrate to a second backside pad, the second backside pad laterally spaced apart from the first backside pad, and the second backside pad separate and distinct from the first backside pad; and
a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.