	US 12,218,039 B2
	Semiconductor package
Jeonggi Jin, Seoul (KR); Gyuho Kang, Cheonan-si (KR); Solji Song, Suwon-si (KR); Un-Byoung Kang, Hwaseong-si (KR); and Ju-Il Choi, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 3, 2023, as Appl. No. 18/311,621.
Application 18/311,621 is a continuation of application No. 17/318,227, filed on May 12, 2021, granted, now 11,676,887.
Claims priority of application No. 10-2020-0115500 (KR), filed on Sep. 9, 2020.
Prior Publication US 2023/0275011 A1, Aug. 31, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01)

CPC H01L 23/49816 (2013.01) [H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01)]

15 Claims

1. A method of a semiconductor package, the method comprising,

forming a redistribution substrate; and

mounting a semiconductor chip on the redistribution substrate,

wherein forming the redistribution substrate comprises:

forming a first redistribution pattern;

forming a recess portion at an upper part of the first redistribution pattern; and

forming a second redistribution pattern on the first redistribution pattern,

wherein the second redistribution pattern includes a via portion and a wire portion on the via portion, the via portion fills the recess portion, and

wherein the recess portion includes an undercut having a downwardly convex bottom surface.