US 12,218,036 B2
Package substrate having integrated passive device(s) between leads
Rajen Manicon Murugan, Dallas, TX (US); and Yiqi Tang, Allen, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Mar. 2, 2023, as Appl. No. 18/177,273.
Application 18/177,273 is a division of application No. 17/233,205, filed on Apr. 16, 2021, granted, now 11,600,555.
Claims priority of provisional application 63/011,296, filed on Apr. 17, 2020.
Prior Publication US 2023/0207430 A1, Jun. 29, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/49534 (2013.01) [H01L 21/4821 (2013.01); H01L 21/563 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/49558 (2013.01); H01L 23/49575 (2013.01); H01L 23/49589 (2013.01); H01L 24/16 (2013.01); H01L 2224/16245 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a multilayer package substrate, comprising:
forming a top layer including top filled vias through a top dielectric layer and a top metal layer providing a top surface of a plurality of leads and a plurality of traces connected to the plurality of leads, and
forming a bottom layer including bottom filled vias including contact pads through a bottom dielectric layer and a bottom metal layer, wherein the top filled vias are for connecting the bottom metal layer to the top metal layer, and wherein the bottom filled vias are for connecting the bottom metal layer to the contact pads;
attaching an integrated circuit (IC) die having a semiconductor surface including circuitry, with nodes in the circuitry electrically connected to bond pads, wherein the IC die is flipchip mounted onto the plurality of leads to provide an electrical connection to the bond pads;
attaching at least one passive device surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the plurality of leads; and
forming a mold compound for encapsulating at least the IC die and the at least one passive device.