US 12,218,021 B2
Semiconductor packages and methods of forming the same
Jung-Wei Cheng, Hsinchu (TW); Jiun-Yi Wu, Taoyuan (TW); Hsin-Yu Pan, Taipei (TW); Tsung-Ding Wang, Tainan (TW); Yu-Min Liang, Taoyuan (TW); and Wei-Yu Chen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 31, 2023, as Appl. No. 18/327,030.
Application 18/327,030 is a continuation of application No. 16/933,910, filed on Jul. 20, 2020, granted, now 11,705,378.
Prior Publication US 2023/0307305 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/40 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/3135 (2013.01) [H01L 23/4012 (2013.01); H01L 23/5383 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a circuit board structure, comprising:
a core layer and first and second build-up layers respectively located on two surfaces of the core layer; and
first conductive patterns located on the first build-up layer;
a first redistribution layer structure disposed over the circuit board structure; and
first bonding elements disposed on the first conductive patterns and located between and electrically connected to the first redistribution layer structure and the circuit board structure,
wherein a portion of an encapsulation layer is disposed between the first redistribution layer structure and the circuit board structure and another portion of the encapsulation layer covers a sidewall of the circuit board structure, and
wherein a sidewall of the first redistribution layer structure is flush with a sidewall of the encapsulation layer.