US 12,218,020 B2
Semiconductor packages
Jiun-Yi Wu, Taoyuan (TW); Chen-Hua Yu, Hsinchu (TW); Chung-Shi Liu, Hsinchu (TW); and Yu-Min Liang, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 16, 2022, as Appl. No. 17/695,864.
Application 17/695,864 is a continuation of application No. 16/655,264, filed on Oct. 17, 2019, granted, now 11,282,761.
Claims priority of provisional application 62/773,139, filed on Nov. 29, 2018.
Prior Publication US 2022/0208633 A1, Jun. 30, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/3135 (2013.01) [H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3142 (2013.01); H01L 24/17 (2013.01); H01L 2224/02335 (2013.01); H01L 2224/12105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a circuit structure;
a first redistribution layer over the circuit structure;
a second redistribution layer over the first redistribution layer;
a first encapsulant, disposed between the first redistribution layer and the second redistribution layer, wherein the first encapsulant comprises a molding compound; and
a bus die and a plurality of through vias surrounding the bus die, wherein the bus die comprises a substrate and a plurality of conductive patterns on the substrate, an entire sidewall of each of the conductive patterns of the bus die is continuous without a turning point, the first encapsulant is a single layer and extended along an entire sidewall of the substrate, the entire sidewall of each of the conductive patterns and an entire sidewall of each of the through vias, and top surfaces of the conductive patterns of the bus die are coplanar with top surfaces of the first encapsulant and the plurality of through vias.