US 12,218,013 B2
Gate structures for semiconductor devices
Chun-Fai Cheng, Tin Shui Wai (HK); Chang-Miao Liu, Hsinchu (TW); and Kuan-Chung Chen, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 9, 2023, as Appl. No. 18/388,419.
Application 18/388,419 is a continuation of application No. 17/461,487, filed on Aug. 30, 2021, granted, now 11,854,906.
Application 17/461,487 is a continuation of application No. 16/835,987, filed on Mar. 31, 2020, granted, now 11,107,736, issued on Aug. 31, 2021.
Prior Publication US 2024/0071835 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/3115 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823857 (2013.01) [H01L 21/02192 (2013.01); H01L 21/02603 (2013.01); H01L 21/28088 (2013.01); H01L 21/28185 (2013.01); H01L 21/31111 (2013.01); H01L 21/3115 (2013.01); H01L 21/823807 (2013.01); H01L 21/823842 (2013.01); H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a nanostructured layer on a substrate;
depositing a high-K gate dielectric layer surrounding the nanostructured layer;
performing a first doping process with a first metal dopant concentration on first and second portions of the high-K gate dielectric layer;
performing a second doping process with a second metal dopant concentration on the first portion of the high-K gate dielectric layer and a third portion of the high-K gate dielectric layer, wherein the second metal dopant concentration is different from the first metal dopant concentration;
depositing a work function metal layer on the high-K gate dielectric layer; and
depositing a gate metal fill layer on the work function metal layer.