US 12,218,011 B2
Method of making 3D segmented devices for enhanced 3D circuit density
Mark Gardner, Cedar Creek, TX (US); and H. Jim Fulford, Marianna, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Nov. 8, 2021, as Appl. No. 17/521,279.
Claims priority of provisional application 63/186,063, filed on May 7, 2021.
Prior Publication US 2022/0359294 A1, Nov. 10, 2022
Int. Cl. H01L 21/82 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/8238 (2013.01) [H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of microfabrication, the method comprising:
forming a layer stack on a substrate, the layer stack including alternating layers of a metal and a first dielectric material;
forming openings in the layer stack that extend vertically through the layer stack and uncover an underlying layer of semiconductor material;
forming vertical channel structures extending through the openings of the layer stack, the vertical channel structures formed by epitaxial growth, the vertical channel structures each having a current flow path that is perpendicular to a surface of the substrate;
segmenting each of the vertical channel structures lengthwise into a plurality of vertical channel structure segments, each vertical channel structure segment having a current flow path that is perpendicular to the surface of the substrate; and
using portions of the layers of the metal to electrically connect to the vertical channel structure segments.